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| verilog (const std::string &filename) |
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const std::string & | design () const |
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const std::vector< std::string > & | inputs () const |
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const std::vector< std::string > & | outputs () const |
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const std::vector< std::string > & | wires () const |
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const std::vector< module > & | modules () const |
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std::size_t | cell_count () const |
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std::size_t | net_count () const |
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std::size_t | pin_count () const |
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The documentation for this class was generated from the following files:
- /home/csguth/workspace/openeda/src/parsing/verilog.h
- /home/csguth/workspace/openeda/src/parsing/verilog.cpp